1. Field of the Invention
The present invention relates to a method for fabricating multilevel interconnects. More particularly, the present invention relates to a method for fabricating a dual damascene structure.
2. Description of the Related Art
Since copper has many good qualities such as a high melting point, a high electromigration resistance and a low resistance, it is widely used in sub-micron process to form multilevel interconnects. However, some problems stated below occur when using copper in sub-micron process. Copper is easily oxidized and eroded. It is difficult to pattern copper by dry etching. The adhesion between copper and dielectric materials is poor. Additionally, copper easily diffuses into the dielectric materials so that the reliability of devices is decreased.
A dual damascene structure is used to solve the above problems. The dual damascene structure is a technique for forming metal interconnects in a dielectric layer. The method for fabricating a dual damascene structure comprises the following steps. A dielectric layer is formed on a substrate, and planarized. The dielectric layer is etched to form a trench and a via hole based on the pattern of connecting wires to be subsequently formed. A copper layer is deposited in the trench and the via hole to form a connecting wire and a via, respectively. Chemical-mechanical polishing is performed to planarize the copper layer. A cap layer is formed on the copper layer. In the dual damascene structure process, etching is not performed, and thus the problem of patterning copper is avoided. Before filling the trench and the via hole with copper, a barrier layer is formed to prevent copper from diffusing into the dielectric layer. The cap layer is formed to prevent the copper layer from oxidizing.
FIGS. 1A through 1C are schematic, cross-sectional diagrams used to depict steps in a conventional method for fabricating a dual damascene structure.
Referring to FIG. 1A, a cap layer 104 and a dielectric layer 106 are formed in sequence on a substrate 100 having a copper layer 102. A trench 108 and a via hole 110, which expose the copper layer 102, are formed in sequence in the dielectric layer 106 and the cap layer 104.
Referring to FIG. 1B, a conformal barrier layer 112 is formed over the substrate 100. A copper layer 114 is formed on the dielectric layer 106 and fills the trench 108 and the via hole 110.
Referring to FIG. 1C, a portion of the copper layer 114 and a portion of the barrier layer 112 are removed by chemical-mechanical polishing to expose the dielectric layer 106.
In the steps mentioned above, the trench 108 and the via hole 110 are formed by reactive ion etching. During the etching process, the copper layer 102 is bombarded so that copper particles are sputtered and deposited on the sidewall of the via hole 110. Furthermore, the copper layer 102 is easily oxidized. To prevent oxides from forming on the copper layer 102 where the oxide would decrease the conductivity of the metal wires, a radio-frequency cleaning process with argon ions is performed to remove the oxides before forming the barrier layer 112. During the cleaning process, copper particles are also possibly sputtered and deposited on the sidewall of the via hole 110. No other materials are formed on the sidewall of the via hole 110 to prevent the copper particles from diffusing into the dielectric layer 106. Thus, the copper particles deposited on the sidewall of the via hole 110 diffuse into the dielectric layer 106 and decrease the reliability of devices.
The barrier layer 112 is made from titanium nitride. However, the adhesion between titanium nitride and copper is poor. Tantalum and tantalum nitride have better adhesion with copper, but only ionized metal plasma technique can form a tantalum layer or a tantalum nitride layer. The step coverage of the ionized metal plasma technique is poor. To obtain enough barrier thickness on the sidewalls of the trench 108 and the via hole 110, a thicker tantalum layer or a tantalum nitride layer must be formed. Because of the poor step coverage of the ionized metal plasma technique, a portion of the tantalum layer or the tantalum nitride layer on the dielectric layer 106 is too thick, although the thickness of the tantalum layer or the tantalum nitride layer formed on sidewalls of the trench 108 and the via hole 110 is just enough. This increases the time for performing chemical-mechanical polishing to remove the redundant tantalum layer or tantalum nitride layer. Furthermore, tantalum and tantalum nitride are both harder than copper, and a dishing effect or an erosion effect that occurs on the copper layer 114 in the trench 108 worsens, as indicated by reference numeral 116 shown in FIG. 1C, after chemical-mechanical polishing.